product brief preliminary chl8112a/b digital multi-phase buck controller trademarks and registered trademarks are the property of th e respective owners. pb 00 12 rev. 0.04, august 25, 2010 page 1 of 2 one highwood drive, tewksbury, ma 01876 tel: +1( 978 )- 640 - 0011 www.chilsemi.com ? 2010 chil semiconductor corp. all rights reserved features 5-phase dual output pwm controller phases are flexibly assigned between loops 1 & 2 amd? svi/g34 & memory mpol modes dual ocp support for i-spike enhanced amd cpus smb_alert pin for servers pmbus address pin or variable gate drive (chl8112a) 2nd temperature sense (chl8112b) overclocking & gaming mode with vmax setting switching frequency from 200khz to 1.2mhz per phase chil efficiency shaping features including variable gate drive (chl8112a only), dynamic phase control programmable 1-phase or 2-phase for light loads and active diode emulation for very light loads chil adaptive transient algorithm (ata) on both loops minimizes output bulk capacitors and system cost designed for use with coupled inductors auto-phase detection with auto-compensation p er -loop fault protection: ovp, uvp, ocp, otp, cfp i2c/smbus/pmbus system interface for telemetry of temperature, voltage, current & power for both loops non-volatile memory (nvm) for custom configuration compatible with chil atl and 3.3v tri-state drivers +3.3v supply voltage; 0oc to 85oc ambient operation pb -free, rohs, 6x6 40 pin qfn package description the chl8112a/b are dual-loop digital multi-phase buck controllers that drive up to 5 phases. the chl8112a/b is fully amd? svi compliant on both loops and provides a vtt tracking function for ddr memory. nvm storage saves pins and enables a small package size. the chl8112a/b includes the chil efficiency shaping technology to deliver exceptional efficiency at minimum cost across the entire load range. chil variable gate drive optimizes the mosfet gate drive voltage as a function of real-time load current. chil dynamic phase control adds/drops active phases based upon load current. the chl8112a/b can be configured to enter 1-phase operation and active diode emulation mode automatically or by command. chils unique adaptive transient algorithm (ata), based on proprietary non-linear digital pwm algorithms, minimizes output bulk capacitors. in addition, a coupled inductor mode, with phases added/dropped in pairs, enables further improvement in transient response and form factor. the i2c/pmbus interface can communicate with up to 16 chl8112a/b based vr loops. device configuration and fault parameters are easily defined using the chil intuitive power designer (ipd) gui and stored in on-chip nvm. the chl8112a/b provides extensive ovp, uvp, ocp and otp fault protection and includes thermistor based temperature sensing with vrhot signal. the chl8112a/b also includes numerous features like register diagnostics for fast design cycles and platform differentiation, truly simplifying vrd design and enabling fastest time- to - market with its set -and- forget methodology. smb_dio pwm5 enable vrtn rcsm isen5 isen4 isen3 vsen smb_clk pwm4 vr_ready 1 / pwrgd 2 irtn3 irtn4 irtn5 rcsp tsen vr_hot# 1 / vrhot_icrit# 2 pwm3 smb_alert# v18a rres vcc isen2 isen1 irtn1 irtn2 pwm2 pwm1 rcsm_l2 rcsp_l2 var_gate_pm_addr (chl8112 a ) tsen2 (chl8112 b ) nc 1 / svd 2 nc 1 / svc 2 nc 1 / vfixen 2 vr_ready_l2 1 / pwrok 2 vcc vinsen vrtn_l2 vsen_l2 1 2 7 8 5 6 3 4 10 9 30 29 24 23 26 25 28 27 21 22 41 gnd chl8112a/b 40 pin 6x6 qfn top view 12 16 14 19 13 17 15 20 18 11 39 35 37 32 38 34 36 31 33 40 notes 1 pin definition in mpol mode 2 pin definition in amd mode figure 1 . chl8112a & chl8112b packages applications amd? svi based systems ddr memory with vtt tracking overclocked & gaming platforms downloaded from: http:///
product brief chl8112a/b digital multi-phase buck controller page 2 o f 2 pb00 12 rev. 0.04 , august 25, 20 10 typical applications block diagrams +3.3v v_cpu_l1 3 28 45 6 16 9 chl8112a 8 11 21 22 23 24 vinsen pwm4 pwm5 pwm3 pwm 2 pwm1 isen5 vr_rdy_l1 1 /pwrgd 2 vsen vcc rres en v18a vrtn irtn3 isen4 2 1 39 irtn1 rcsp irtn2 rcsm isen3 isen2 isen1 irtn4 +12v v from system l o a d rcs ccs r series r series r th r vin_1 r vin_2 37 38 35 36 33 34 irtn5 25 31 32 10 vr_rdy_l2 1 /pwrok 2 tsen r th2 7 gnd 40 hvcc logate higate vcc gnd pwm lvcc 12v v boot switch v v_vgd chl8510 hvcc logate higate vcc gnd pwm lvcc 12v v boot switch v v_vgd chl8510 hvcc logate higate vcc gnd pwm lvcc 12v v boot switch v v_vgd chl8510 hvcc logate higate vcc gnd pwm lvcc 12v v boot switch v v_vgd chl8510 hvcc logate higate vcc gnd pwm lvcc 12v v boot switch v v_vgd chl8510 hvcc logate higate vcc gnd pwm lvcc 12v v boot switch chl8510 v_vgd 20 var_gate_ pm_addr optional variable gate drive circuit v_cpu_l2 l o a d 15 vr_hot# 1 / vrhot_icrit# 2 17 +3.3v 18 19 smb_clk smb_dio smbus v v v smb_alert# 29 30 rcsp_l2 rcsm_l2 rcs ccs r series r series r th 27 26 vsen_l2 vrtn_l2 17 18 19 nc 1 /svc 2 nc 1 /svd 2 v v v nc 1 /vfixen 2 cpu serial bus notes 1 pin definition in mpol mode 2 pin definition in amd mode ordering information chl8112 ? - ? ? ? ? ? package tape & reel qty part number qfn 3000 chl8112a-00crt 1 qfn 3000 chl8112a-xxcrt 2 qf n 3000 CHL8112B-00CRT 1 qfn 3000 chl8112b-xxcrt 2 notes 1. for unprogrammed/default parts, use configuration file 00. unprogrammed parts will not start up until programmed in order to insure a safe power up. 2. -xx indicates a customer specific configuration file t: tape & reel xx: configuration file operating temperature c: commercial standard package type r : qfn part a: chl8112a b: chl8112b downloaded from: http:///
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